In an active cycle of a synchronous Dynamic Random Access Memory (DRAM) a word line is selected by a row address and a bit line is selected by a column address which is generated by an address counter. Data can be written to or read from the memory cell that is positioned at a cross point of the selected word line and bit line. In a synchronous DRAM the column address is generated through an address counter because in many cases the input and output of data is continuously conducted in a burst fashion. Only a start address for reading and writing is given externally and a subsequent address is generated by the address counter. The continuous read operation is known as a "burst read", and the continuous write operation is known as a "burst write." The number of data continuously read or written is known as a "burst length."
The burst length can be set in a programmable fashion with typical lengths being 2, 4, or 8 bit lengths. For example, in the case where the burst length is four and the start address is 3, the address counter outputs the addresses to the column decoder in the order of 3, 0, 1, and 2. In the case of a burst length of four, the specification of the synchronous DRAM designates the two lowest significant bits of the address to be incremented through the counter while the more significant address bits are not changed.
Referring to FIG. 12, a memory address generator circuit for conducting reading and writing operations as described above is set forth. The memory address generator circuit is designated by the general reference character 1200 and includes an address counter 1204 that generates a column address and a burst counter 1206 that counts the burst length. The memory address generator circuit 1200 further includes an address latch 1202 that latches an externally applied address.
In the memory address generator circuit 1200, an externally applied address is latched by the address latch 1202 and applied to the address counter 1204 as a start address. After the start address has been set, the address counter 1204 increments the address by one upon receiving subsequent clock (CLK) signals. The address counter 1204 applies its output to a column decoder (not shown) which generates a column select signal.
The burst counter 1206 is reset every time a read or write command is input thereto and increments by one every clock cycle. Given a burst length of 2.sup.n (n=1, 2, 3), the burst counter 1206 generates a burst end (BSTEND) signal when all the n least significant bits of the burst counter 1206 are ones. The BSTEND signal is generated to signal the end of the burst read or burst write operation.
The memory address generator circuit 1200 shown in FIG. 12 is relatively large because it requires both an address counter 1204 and a burst counter 1206. However, a semiconductor memory device having a memory address generator circuit with only one counter as the address generator is disclosed in Japanese Unexamined Publication No. Hei 8-339686.
Referring to FIG. 13, a block schematic diagram of a semiconductor memory device, according to the above publication, is set forth. The semiconductor memory device is designated by the general reference character 1300 and includes memory blocks 1302a and 1302b. Each memory block 1302a and 1302b contains a plurality of memory cells (one of which is shown as 1304) in which data is stored. The semiconductor memory device 1300 further includes a row decoder 1306, which receives and decodes row address information and activates a main word line (MWL1 and MWL2). A sub-decoder (one of which is shown as 1308) receives the main word line and a memory block select signal and activates a sub-word line (SWL1-SWL4) in a selected memory block 1302a and 1302b.
Further included in the semiconductor memory device 1300 is a flag register 1310. The flag register 1310 stores a continuous read flag indicative of the maximum number of data to be continuously read. Further included is a cycle counter 1312, which refers to the value of the flag register 1310 and increments (or decrements) in synchronism with a clock (CLK).
An access control circuit 1314 controls the row decoder 1306 and a pre-charge circuit 1316. The pre-charge circuit 1316 charges the bit lines (BL1-BL4) to a predetermined pre-charge voltage level. An output control circuit 1318 decodes column address information and controls a column selector circuit 1320 and sub-decoders 1308. A column selector circuit 1320 selects the bit line (BL1-BL4) to be accessed during the active cycle. The column selector circuit 1320 is coupled to an output circuit 1322, which outputs the read data externally from the semiconductor memory device 1300.
Referring to FIG. 13, a description will be given of the burst operation of the semiconductor memory device 1300. In the example, it is assumed that the start address information, in response to an access command, activates the main word line MWL1. Furthermore, the start address information corresponds to an initial column address 0. In an initial memory access cycle the cycle counter 1312 is cleared or set to zero. Also, in the initial memory access cycle, the number of data bits to be continuously read is two and the flag register 1310 is set accordingly. In response to the start address information and the cycle counter value, the row decoder 1306 selects the main word line MWL1 and the output control circuit 1318 activates a memory block select signal that corresponds with memory block 1302a. As a result, sub-word line SWL1 is activated and data in the memory cell 1304 of the memory block 1302a is read and then outputted from the bit lines (BL1 and BL2) through the column selector circuit 1320 and the output circuit 1322.
In a succeeding memory access cycle, the value of the cycle counter 1312 is incremented thus becoming a value of one. Thus, the output control circuit 1318 causes the sub-word line SWL2 in memory block 1302b to be activated. As a result, data in a memory cell 1304 of the memory block 1302b is read and then outputted from the bit lines (BL3 and BL4) through the column selector circuit 1320 and the output circuit 1322.
The value of the flag register 1310 is held during the continuous memory reading operation and the flag register 1310 is not cleared until the value of the cycle counter 1312 reaches the number of data to be read minus one.
In the approach set forth in FIG. 13, the column address in the semiconductor memory device 1300 is determined according to the applied external start address and the value in the cycle counter 1312. The cycle counter value is incremented (or decremented) from zero so that the operation of the cycle counter 1312 is allowed to stop in accordance with the burst length. Data can be read for each of the burst lengths by giving only the external start address. However, in order to generate the column address, the addition of the start address and the cycle counter value must be made.
Generally, an adder circuit consumes a lot of chip space. Also, an adder circuit is typically slow in operational speed because of the carry requirement, and is particularly slow when a large number of digits are added. The semiconductor memory device 1300 set forth in FIG. 13 suffers from the drawbacks that the address generation circuitry becomes relatively large and is slow in operation, which reduces the operation speed of the memory. Additionally, the adder circuit causes an increase in the semiconductor memory device's power consumption.
In light of the aforementioned problems with the prior art approach of memory address generation, it would be desirable to provide a memory address generator circuit to be used in a semiconductor memory device for conducting reading and writing operation in a burst fashion, with improved operational speed. At the same time the memory address generator should not consume a lot of chip space or greatly increase the chip's power consumption.